std :: kernel::mmu
Struct std::MmuContext
generic<F: MmuFormat> struct MmuContext {
unsigned long root;
unsigned long phys_offset;
&static FrameAllocator frames;
F fmt;
}Fields
physical address of the root table
tables live at phys + phys_offset
source of new intermediate tables
Methods
static struct MmuContext<F> new(
unsigned long root,
&static FrameAllocator frames,
unsigned long phys_offset,
)source · definitionA context over an existing root table at physical 'root' — zeroed, and aligned as the format needs (4 KiB; 16 KiB for MmuArmV7). 'frames' must be a live, &static-lifetime FrameAllocator (the kernel's own, usually); frame f's table memory is at frames.frame_addr(f) + phys_offset. F comes from the target type:
struct MmuContext<MmuNative> mmu = std::MmuContext::new(root, &g_frames, 0UL);
Map the 4 KiB page at 'virt' to 'phys' (both 4 KiB aligned; low bits ignored) with MMU_* flags, allocating intermediate tables as needed. Returns 1, or 0 if a table frame couldn't be allocated or a larger leaf already covers 'virt'. Remapping a page overwrites it; flush the TLB entry afterwards if the context is live.
Remove the page at 'virt' (no-op if unmapped). Tables aren't freed.
Resolve 'virt': 1 and *phys_out on success, 0 if unmapped.
The raw leaf entry mapping 'virt': 1 and *entry_out, or 0 if unmapped.
TLB maintenance and switching to this address space: x86 reloads CR3 / invlpg; RISC-V writes satp (which also turns translation on for S/U mode) / sfence.vma; AArch64 writes TTBR0_EL1 / TLBI; ARMv7 writes TTBR0 / TLBIALL. Turning paging on (CR0.PG, SCTLR.M) and the MAIR/TCR setup are the boot code's. Each returns 1 if it ran, 0 if F isn't the running CPU's format (or in a hosted process).