Module kernel::mmu

MMU Context (real hardware page tables) Virtual-to-physical address translation for freestanding targets. Freestanding-safe; TLB/activate operations use inline asm inside unsafe{}.

MmuContext<F> builds the page tables the CPU itself walks. F is a compile-time page-table format type — every table walk step is a direct, inlinable call to F's methods, the same pattern as BST<K, V, C>'s ordering. One format per architecture:

MmuX86_64   x86-64 4-level paging (48-bit VA; PML4/PDPT/PD/PT, 8-byte entries)
MmuX86_32   x86 32-bit paging without PAE (2 levels, 4-byte entries)
MmuSv39     RISC-V Sv39 (RV64, 3 levels, 8-byte PTEs)
MmuSv32     RISC-V Sv32 (RV32, 2 levels, 4-byte PTEs)
MmuAArch64  AArch64 stage 1, 4 KiB granule, 48-bit VA (4 levels)
MmuArmV7    ARMv7-A short-descriptor (4096-entry L1 + 256-entry L2)

MmuNative names the format of the CPU being compiled for (none on Cortex-M, which has an MPU but no MMU, or on wasm). All formats can be built and walked on any target — e.g. on the host, for tests or for an image builder — but activate()/tlb_flush_*() only touch the CPU when the format matches the running bare-metal target (they return 0 otherwise, and always in a hosted process).

Mappings are 4 KiB pages. walk() also follows larger (block/superpage) leaves built by someone else.

Tables are read and written at (physical address + phys_offset): 0 for an identity-mapped kernel, the direct-map base for a higher-half one. New intermediate tables come from 'frames' (one 4 KiB frame each, zeroed); the root table is the caller's.