Module simd::riscv

std::simd, RISC-V convenience layer

Pure naming/documentation layer over std/simd/simd.h's portable vec<T,N>-based types and functions — LLVM's RISC-V backend lowers every operation in simd.sc to real V-extension (RVV) instructions (vsetivli, vfadd.vv, vle32.v/vse32.v, ...) when the target has '+v' enabled, from the portable source; there is no separate hand-written implementation.

Important difference from x86_64/AArch64/WASM: RVV registers are scalable (VLEN is implementation-defined, not fixed by the ISA), so there is no single "native width" the way SSE=128-bit or NEON=128-bit is. SafeC's vec<T,N> is a fixed-width type (N is a compile-time constant lane count, matching LLVM's fixed-vector IR), so these aliases pick a commonly-supported baseline (VLEN=128, the minimum required by the RVV 1.0 'V' extension's zvl128b requirement) rather than modeling true scalable vectors — LLVM still generates correct RVV code for a fixed-width vec<T,N> (as the vsetivli-prefixed instructions above show), it just fixes the vector length at compile time instead of querying it at runtime via vsetvli the way idiomatic scalable-RVV C code would.